Interfacing (DSI, CSI, I2C, etc.) • Re: PWM phase offsets not working on RP1

Unfortunately there's quite a few bugs around phase shifting - it only works in some modes, and can only be set before the channels are enabled. Ironically, the long-form description is correct and the register descriptions aren't.

Trailing-edge is one of the modes that should work.

Edit: it's even more complicated than that. To shuffle the offset into the correct internal register there's a painful dance that needs to be done -

• Initialise PHASE to required eventual number
• Set RANGE to a large number (such that polling the channel overflow flag in software will reliably catch an overflow)
• Set DUTY to 0
• Set MODE to trailing-edge
• Enable channel
• Wait for channel overflow
• Set MODE to leading-edge / write 1 to SET_UPDATE
• wait for channel overflow
• Set MODE to trailing-edge / write 1 to SET_UPDATE
• Set RANGE to the required number
• Wait a sufficiently long period such that at least 1 overflow occurrs
• Write nonzero duty cycles.

RANGE and DUTY are synchronously updated on overflow. The fact that PHASE isn't, and requires an enforced period of no output before a different phase offset can be established, probably torpedoes any application where it needs frequent updates. There's also critical periods around internal counts of 0 / DUTY / RANGE where a channel MODE update would cause the counter to never overflow.

Statistics: Posted by jdb — Wed Jul 31, 2024 12:26 pm

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