The idea with dummy byte is as below:XL_X_L_1 - first sample of lower byte of X axis,
XL_X_H_1 - first sample of upper byte of X axis and so on for Y, and Z, and will wrap for second, third and nth sample of FIFO.
So my working configuration. As presented above, TX channel is not incrementing, it is sending the samy byte all over again, but it has to do that. TX and RX channels have the samy transfer number defined:Buffer needs to be one byte larger, to accommodate that dumy byte. dma_channel_wait_for_finish_blocking() might be ditched when using interrupt to start transfer or sth. And because of that, gpio_put(CS, 1); is on top, then using contents of while loop inside a timer or sht - so CS is on most of the time, not to off CS right after DMA has started.
PS. That DMA chaining idea doesn't work - at least for BMI160.
Code:
0 , 1 , 2 , 3 , 4 TX (MOSI): FIFO_REG | 0x80, FIFO_REG | 0x80, FIFO_REG | 0x80, FIFO_REG | 0x80, FIFO_REG | 0x80RX (MISO): DUMMY_BYTE , XL_X_L_1 , XL_X_H_1 , XL_Y_L_1 , XL_Y_H_1XL_X_H_1 - first sample of upper byte of X axis and so on for Y, and Z, and will wrap for second, third and nth sample of FIFO.
So my working configuration. As presented above, TX channel is not incrementing, it is sending the samy byte all over again, but it has to do that. TX and RX channels have the samy transfer number defined:
Code:
uint dma_tx = dma_claim_unused_channel(true);uint dma_rx = dma_claim_unused_channel(true);dma_channel_config c_tx = dma_channel_get_default_config(dma_tx);channel_config_set_transfer_data_size(&c_tx, DMA_SIZE_8);channel_config_set_dreq(&c_tx, spi_get_dreq(SPI, true));channel_config_set_read_increment(&c_tx, false);channel_config_set_write_increment(&c_tx, false);dma_channel_config c_rx = dma_channel_get_default_config(dma_rx);channel_config_set_transfer_data_size(&c_rx, DMA_SIZE_8);channel_config_set_dreq(&c_rx, spi_get_dreq(SPI, false));channel_config_set_read_increment(&c_rx, false);channel_config_set_write_increment(&c_rx, true);while (true) {gpio_put(CS, 1);dma_channel_configure(dma_tx, &c_tx, &spi_get_hw(SPI)->dr, &fifo_register_for_read,FIFO_NUMBER_OF_BYTES + 1, false);dma_channel_configure(dma_rx, &c_rx, buffer, &spi_get_hw(SPI)->dr, FIFO_NUMBER_OF_BYTES + 1, false);gpio_put(CS, 0);dma_start_channel_mask((1u << dma_tx) | (1u << dma_rx));dma_channel_wait_for_finish_blocking(dma_rx);sleep_ms(5000);}PS. That DMA chaining idea doesn't work - at least for BMI160.
Statistics: Posted by MatSOBDev2 — Wed Aug 07, 2024 1:02 pm
