I am not sure yet, it could be something related to the board definition. It's quite intricate how (but understandable why) SDK changes frequencies, especially with overclocking and custom boards. Need to dig more.
But I think I found a reason why it works well with original Pico 2, by default, but needs signal tuning on others. One difference is that the custom boards have PSRAM connected to the same bus with Flash. It creates an increased dynamic load on the data and clock lines, with a small delay added (by slowing the level transition time), which needs to be compensated at high frequencies (above 100 MHz). It can be done tuning the read time (half a clock looks enough), or maybe changing the drive strength (it has 2 loads instead of 1). The load on data/clock lines doesn't simply disappear when the PSRAM is disabled/disconnected only by CS signal, the rest of the lines remain physically still connected.
But I think I found a reason why it works well with original Pico 2, by default, but needs signal tuning on others. One difference is that the custom boards have PSRAM connected to the same bus with Flash. It creates an increased dynamic load on the data and clock lines, with a small delay added (by slowing the level transition time), which needs to be compensated at high frequencies (above 100 MHz). It can be done tuning the read time (half a clock looks enough), or maybe changing the drive strength (it has 2 loads instead of 1). The load on data/clock lines doesn't simply disappear when the PSRAM is disabled/disconnected only by CS signal, the rest of the lines remain physically still connected.
Statistics: Posted by gmx — Sat Sep 14, 2024 10:16 pm