Arg001, please forgive me for being naive. I have some answers to your questions.Sadly, you don't seem to have taken on board the advice I gave you last time - GROUND IS IMPORTANT!
At least in the zoomed-in plots, there is no connection at all between the ground on the left-hand half of the picture (where most of the decoupling caps are) and the right hand side (where the RP2040 ground pad is connected). So most of your decoupling will be ineffective - C12 and C16 will be doing all the work and the others might as well not be there. What matters with decoupling is the length of the complete loop: from capacitor +ve end, to the RP2040 pin, through the RP2040 itself, out through the ground pad on the bottom of the RP2040 and back to the -ve end. Those loops should be as short as possible. On a typical RP2040 board where the CPU is much faster than the I/O devices, those connections should be the first thing on your design and everything else fits around them (power/ground, then flash chip, then crystal, then I/O is the order of priority).
That much wouldn't be enough to stop it booting, just give poor performance, but I'm also wondering whether that ground island around the flash chip/decouplers is in fact connected to ground on the rest of the board at all. I can see a couple of ground jumpers bridging the split in the groundplane caused by the USB tracks, so maybe you've taken care of that, but the ones I can see aren't enough, there would need to be more off to the left of the picture (and for some reason you seem to have chosen to flood-fill with VBUS rather than GND on the blue side).
After double checking with a multimeter, the ground on the left column of capacitors is in fact connected to the ground on the right column, and I managed to figure out how to highlight nets to show you a picture.
I understand now, thanks to you, that by not having the ground plane below the rp2040 and the ground plane to the left of it connected, there could be some inefficiencies. However, I am still confused at why the 1.1v net is floating. On the design documentation, I know it mentions that in order for the regulator to work, there must be 1μF capacitors close to both VREG_IN and VREG_OUT. I double checked and I can say for sure that the capacitors I put there are 1μF, the same ones on the prototype. Shorting the ground between the VREG decouplers and the capacitors near the crystal also does not seem to help.
I hope these pictures help, and if you would like more please let me know!
Statistics: Posted by naquino14 — Wed Oct 02, 2024 11:14 pm