The two 'banks' are the normal GPIOs (GPIO0-29), and the pins associated with the QSPI flash (which can also be used as GPIOs if you are not using the flash).That sounds like four interrupts for GPIO, not one. Though they only seem to document one for each core2.3.2. Interrupts
Each core is equipped with a standard ARM Nested Vectored Interrupt Controller (NVIC) which has 32 interrupt inputs.
Each NVIC has the same interrupts routed to it, with the exception of the GPIO interrupts: there is one GPIO interrupt per
bank, per core. These are completely independent, so e.g. core 0 can be interrupted by GPIO 0 in bank 0, and core 1 by
GPIO 1 in the same bank.
13 IO_IRQ_BANK0.
15 SIO_IRQ_PROC0
16 SIO_IRQ_PROC1
Not clear.
So for most purposes, there is only one GPIO IRQ per CPU core. The other one does exist - it's number 14, "IO_IRQ_QSPI", but since most applications (and certainly those on a Pico) reserve those pins for flash, it's not useful. If building your own PCB, you could either limit the flash to standard SPI rather than QSPI, thus freeing up two pins to use as GPIO, or arrange some multiplexing so you can boot from the flash and then use the all pins as GPIOs with the software running from RAM.
The single IO_IRQ_BANK0 is special however - all the other non-GPIO interrupts are just wired in parallel to the two CPU cores (in the expectation that you enable it on one core or the other but usually not both). In the GPIO case, the GPIO peripheral has separate enable registers for each CPU, and the two CPUs each get a separate interrupt signal for whichever GPIO events have been enabled for that CPU.
Statistics: Posted by arg001 — Tue Aug 06, 2024 1:52 pm